7.3 Microprogrammed Control Units: Horizontal vs Vertical Micro-Instructions

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📚07Topic 7.3⏱️35 min

🎯High-Yield For:Microprogrammed control units form the architectural foundation of complex CISC processors, allowing rich instruction sets to be synthesized via structured microcode firmware stored in ROM. Mastering horizontal vs vertical formats, sequencer branch mechanics, and two-level nano-programming is essential for modern CPU microarchitecture.

💡 Core Intuition: Software Inside Silicon

As computer architectures evolved throughout the 1950s and 1960s, instruction sets grew dramatically in complexity. Implementing hundreds of multi-byte, multi-addressing-mode instructions purely with combinational AND-OR logic gates (hardwired control) resulted in an unmaintainable "rat's nest" of silicon interconnects. A single bug or instruction format revision required scrap-heaping physical silicon masks and redesigning the entire chip layout.

In 1951, Maurice Wilkes proposed an elegant, revolutionary paradigm: Microprogramming.

Instead of generating control signals through fixed physical wiring, treat the control unit as an internal computer within a computer. The hardware control signals required for each clock cycle are stored as binary words (micro-instructions) inside a specialized, ultra-fast read-only memory called Control Memory (CM).

🍳 The Everyday Analogy: The Digital Synthesizer vs. The Piano

• Hardwired Control is an Acoustic Piano: When you press key C4, a physical felt hammer strikes steel strings directly. It produces sound at the speed of mechanical physics (zero latency). But if you want the piano to sound like an electric guitar or an orchestral flute, you must throw the piano away and rebuild a completely different acoustic instrument.
• Microprogrammed Control is a Digital MIDI Synthesizer: When you press key C4, a processor looks up a row of binary data in a memory bank (the sound sample / microcode word), which tells the digital-to-analog converter exactly how to shape the audio waveforms.
  • To add a new instrument or patch a flawed tone, you do not touch a soldering iron—you simply load a new firmware file into the synthesizer's memory!
  • The trade-off: Looking up sound samples in memory takes a few extra clock cycles compared to a mechanical hammer strike.

Architecture Flow

Microprogrammed Control Address & Execution Pipeline

How opcodes map into control memory addresses to drive datapath control vectors

📜Instruction Phase

Opcode Mapping Logic

Translates machine instruction opcode bits into the base address of its microcode routine.

→

Starting Address

📫Addressing

Control Address Register (CAR)

Holds the k-bit address of the next micro-instruction to be read from ROM.

→

Address Lines

💾Control Store

Control Memory (CM / ROM)

Fast on-die memory storing the pre-programmed microcode words.

→

Control Word

📦Execution Latch

Control Data Register (CDR)

Latches the active micro-instruction; asserts datapath enables and feeds next-address sequencer.

💻 Bridging to Computer Science

In a microprogrammed architecture:

• A Micro-operation is an atomic hardware action (e.g., $AR \leftarrow PC$ or $DR \leftarrow M[AR]$).
• A Micro-instruction is a control word stored in Control Memory whose bit pattern specifies one or more micro-operations to be executed simultaneously during a single clock cycle, along with sequencing information.
• A Micro-program (or Microcode Routine) is a sequential routine of micro-instructions that implements the complete fetch, decode, and execution lifecycle of a single machine-language instruction.

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📑Table of Contents

• 🏛️ Architecture of a Microprogrammed Control Unit
  • Microprogram Sequencing Logic & Address Sources
• 🔀 Horizontal vs. Vertical Microprogramming
  • Anatomy of Micro-Instruction Formats
  • Detailed Architectural Trade-Off Matrix
• 🗄️ Two-Level Control Store: Nano-Programming
  • Architectural Mechanics
• 🏭 Real-World Production Context: Modern Microcode Engines
• 📐 Numerical Applications & Worked Examples
  • Example 1: Control Memory Sizing for Horizontal Microprogrammed Processor
  • Example 2: Vertical Microprogramming Grouping & Bit Compression Analysis
  • Example 3: Microinstruction Field Allocation & CAR Sizing
• 🎯 Exam & Interview Pitfall Check

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🏛️ Architecture of a Microprogrammed Control Unit

A microprogrammed control unit is structured around four primary hardware units:

Microprogrammed Control Unit Hardware Organization

Core architectural building blocks coordinating microcode sequencing and execution

💾

Control Memory (CM / ROM)

2^k Words x W Bits

• Dedicated ultra-fast read-only storage holding all machine micro-routines.
• Stores fetch, indirect, and execution micro-instruction sequences.
• Cycle time matches the CPU execution clock for zero wait-state reads.

📫

Control Address Register (CAR)

k Bits Wide

• The microcode equivalent of the Program Counter (PC).
• Holds the k-bit physical address pointing to the active micro-instruction in CM.
• Synchronously advances via CAR + 1 or loads jump/mapping target addresses.

📦

Control Data Register (CDR / CBR)

W Bits Wide

• Also designated as the Control Buffer Register (CBR) or Micro-Instruction Register.
• Latches the micro-instruction word read from Control Memory on the clock edge.
• Partitions bits into datapath control enables and sequencer branch fields.

🔀

Microprogram Sequencer

Next-Address Logic

• Arbitrates and selects among four next-address sources driving the CAR.
• Supports sequential increment, conditional branch, subroutine call, and opcode mapping.
• Interfaces directly with processor status condition flags (Z, S, C, V).

Microprogram Sequencing Logic & Address Sources

The Microprogram Sequencer generates the next CAR address by multiplexing four distinct inputs:

Four Next-Address Sources in the Microprogram Sequencer

1

Sequential Step (CAR + 1)

Advances linearly to the next consecutive micro-instruction in the current micro-routine.

2

Branch / Jump Target

Loads the target address field directly from the Control Data Register when a branch condition is met.

3

Opcode Mapping Logic

Transforms the machine instruction opcode into the starting address of its corresponding microcode routine.

4

Subroutine Return (SBR)

Restores the return address popped from the Subroutine Register after completing a shared micro-subroutine.

Opcode Mapping Mechanics

When an instruction is fetched into the processor's Instruction Register ($IR$), the control unit must jump to the beginning of that instruction's specific micro-routine in Control Memory.

In a computer with a 4-bit opcode ($IR_{14\text{--}11}$) and a 7-bit CAR ($128 \text{ words}$ in control memory), a simple mapping logic circuit prepends a $0$ and appends $00_2$ to the opcode:

$$\text{Mapping: } \quad 0 \; \underbrace{IR_{14} \; IR_{13} \; IR_{12} \; IR_{11}}_{\text{4-bit Opcode}} \; 0 \; 0$$

This maps 16 distinct opcodes to starting addresses $0, 4, 8, 12, \dots, 60$ in Control Memory, allocating up to 4 micro-instructions per routine! If a routine requires more than 4 micro-instructions, it can branch to an unmapped upper memory space ($64 \text{ to } 127$).

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🔀 Horizontal vs. Vertical Microprogramming

The structure of the micro-instruction control field establishes the fundamental classification of microprogrammed control units:

Horizontal vs. Vertical Microprogramming Paradigms

The fundamental architectural trade-off between control word width and hardware decoder latency

Direct & Parallel

Horizontal Microprogramming

↔️

Dominant Architecture / DomainVLIW Processors, High-Speed DSPs & Supercomputers

• •Every control signal in the CPU has a dedicated 1-bit position in the control word.
• •Extremely wide control words (typically 50 to 128+ bits).
• •Maximum degree of parallelism: multiple non-conflicting control signals assert in one cycle.
• •Zero decoding hardware: control bits connect directly to register enables and ALU pins.
• •Fastest micro-execution time, but lower memory storage efficiency.

"Maximizes hardware parallelism by dedicating one unencoded control bit to every datapath line."

Encoded & Compact

Vertical Microprogramming

↕️

Dominant Architecture / DomainCISC Processors & Embedded Microcontrollers

• •Mutually exclusive control signals are grouped and binary-encoded into compact fields.
• •Narrow control words (typically 16 to 32 bits).
• •Restricted parallelism: at most one signal per group can be active per clock cycle.
• •Requires external decoders at the output of the Control Data Register.
• •Highly compact control memory, but introduces decoder propagation delay.

"Compresses control store footprint by encoding mutually exclusive signals into compact bit fields."

Anatomy of Micro-Instruction Formats

1. Horizontal Micro-Instruction Format

In pure horizontal microprogramming, no decoding is performed. For a processor with $N$ hardware control signals:

Direct Unencoded FormatTotal Frame: 64 Bits

Horizontal Micro-Instruction Word Layout

Unencoded direct control bit vector with integrated sequencer branch logic

Control Signals Field

48 Bits

48 Bits Direct

[63:16]

Condition Select

4 Bits

4 Bits MUX

[15:12]

Branch Address

12 Bits

12 Bits CAR

[11:0]

48 Bits48 Bits DirectControl Signals Field

Unencoded direct control outputs driving datapath signals (PC_out, AR_in, DR_load, ALU_add) with zero decoding delay.

2. Vertical Micro-Instruction Format

In vertical microprogramming, control signals that can never be asserted simultaneously (mutually exclusive signals, such as bus drivers or ALU functions) are grouped together.

If group $i$ contains $k_i$ control signals, we must encode both the $k_i$ active signals plus one state representing No-Operation (NOP):

📐Vertical Group Bit Width Formulatheorem

$$\text{Bits for Group } i = \left\lceil \log_2(k_i + 1) \right\rceil$$

Hardware Invariant: The extra $+1$ state is strictly mandatory so that the group can remain inactive ($00\dots0_2 = \text{NOP}$) when none of its control signals are needed during a cycle.

Field-Encoded FormatTotal Frame: 28 Bits

Vertical Encoded Micro-Instruction Word Layout

Encoded functional control fields with dedicated external decoders and sequencer branch fields

Group A (ALU)

4 Bits

4 Bits (16 states)

[27:24]

Group B (Bus Src)

3 Bits

3 Bits (8 states)

[23:21]

Group C (Dest Reg)

4 Bits

4 Bits (16 states)

[20:17]

Condition MUX

3 Bits

3 Bits (8 flags)

[16:14]

Branch Address

10 Bits

10 Bits (1024 words)

[13:4]

Branch Opcode

4 Bits

4 Bits (16 ops)

[3:0]

4 Bits4 Bits (16 states)Group A (ALU)

Decoded via 4x16 external decoder into 15 distinct arithmetic/logic micro-operations plus 1 NOP code.

Detailed Architectural Trade-Off Matrix

Metric / Parameter	Horizontal Microprogramming	Vertical Microprogramming
Control Word Width	Very Wide ($50 \text{ to } 128+ \text{ bits}$)	Narrow ($16 \text{ to } 32 \text{ bits}$)
Degree of Parallelism	Maximum (All independent signals active)	Low / Restricted (At most 1 signal per group)
Control Memory Size (Bits)	Large ($\text{Words} \times \text{Wide Word}$)	Small ($\text{Words} \times \text{Narrow Word}$)
Decoding Circuitry Required	None (Direct bit-to-pin wiring)	Required (Decoders for each group)
Propagation Delay Overhead	Zero decoding delay ($t_{\text{dec}} = 0$)	Adds decoder latency ($t_{\text{dec}} \approx 0.5\text{--}1.5 \text{ ns}$)
Execution Cycle Speed	Faster per micro-instruction	Slower due to sequentialization
Design Flexibility	High (Any signal can be added)	Moderate (Adding signals alters field widths)
Primary Domain	VLIW, high-speed DSPs, signal processors	CISC processors, cost-constrained microcontrollers

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🗄️ Two-Level Control Store: Nano-Programming

In complex CISC processors (such as the Motorola 68000), analyzing horizontal control memory reveals massive redundancy: across thousands of micro-instructions, only a small subset of distinct control signal combinations are ever used.

To eliminate this redundancy without sacrificing horizontal parallelism, designers invented Nano-Programming (Two-Level Control Store):

Architecture Flow

Two-Level Nano-Programming Architecture

Decoupling microcode sequencing from wide horizontal control vector generation

🧭Sequencing (Level 1)

Micro-Store (μROM)

Stores W words containing next-address sequencing fields and a narrow pointer (Nano-Address).

→

Nano-Address (log2 U bits)

💾Control Generation (Level 2)

Nano-Store (NanoROM)

Stores only U unique control words (U << W), holding the full C-bit horizontal control vector.

→

C-Bit Control Vector

⚡Silicon Execution

Processor Datapath

Directly asserts unencoded control signals across ALU, bus multiplexers, and register latches.

Architectural Mechanics

1. Level 1: Micro-Store ($\mu$ROM):
   • Contains $W$ words (total number of micro-instructions in all routines).
   • Each word does not contain control signals. Instead, it contains a short pointer: the Nano-Address pointing to a unique entry in Level 2, plus next-address sequencing fields.
2. Level 2: Nano-Store (NanoROM):
   • Contains only the $U$ unique horizontal control words actually used by the processor ($U \ll W$).
   • Each word is $C$ bits wide (the full horizontal control width).

📐Nano-Programming Memory Savings Prooftheorem

For a system with $W$ total micro-instructions, $U$ unique control vectors, and horizontal control word width $C$:

$$\text{Single-Level Memory Bits} = W \times C$$$$\text{Two-Level Memory Bits} = \left( W \times \left\lceil \log_2 U \right\rceil \right) + (U \times C)$$$$\mathbf{\text{Memory Savings}} = (W \times C) - \left[ W \cdot \lceil \log_2 U \rceil + U \cdot C \right]$$

When $W = 2048$, $U = 256$, and $C = 128 \text{ bits}$:

• Single-Level CM: $2048 \times 128 = 262,144 \text{ bits}$ ($32 \text{ KB}$).
• Two-Level CM: $(2048 \times \lceil \log_2 256 \rceil) + (256 \times 128) = (2048 \times 8) + 32,768 = 16,384 + 32,768 = 49,152 \text{ bits}$ ($6 \text{ KB}$).
• Silicon Area Reduction = $81.25\%$!

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🏭 Real-World Production Context: Modern Microcode Engines

In modern computing, microprogramming is the linchpin enabling the survival and security of the x86 ecosystem:

Real-World CPU Control Unit Hierarchy

How modern processor architectures blend hardwired speed with microcode patchability.

Software Patch Layer

Operating System & BIOS Microcode Update Engine

🛡️

Linux and Windows kernel loaders apply cryptographically signed Intel/AMD microcode patches directly into CPU SRAM at boot time to patch hardware security vulnerabilities.

Spectre / Meltdown MitigationsDownfall / Zenbleed Microcode PatchesZero Silicon Re-Spin Cost

↓Pushed to Control Unit Writable SRAM

CISC Emulation

Microcode Sequencer ROM (Intel Raptor Lake / AMD Zen 4 MSROM)

⚙️

Complex x86 instructions (e.g., string copy MOVS, task switch, context save) invoke multi-hundred cycle microcode routines stored in on-die high-density ROM.

Complex State SequencingDeterministic Fault Trappingx86 Backward Compatibility

↓Decodes into RISC-like Micro-ops

Fast-Path Silicon

Hardwired RISC Execution Core

⚡

90%+ of typical application instructions (ADD, MOV, XOR, JMP) bypass the microcode ROM completely, translated by 4-wide hardwired fast-path decoders in 1 cycle.

Direct Micro-op Emission1-Cycle Decode Latency5+ GHz Clock Scaling

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📐 Numerical Applications & Worked Examples

Example 1: Control Memory Sizing for Horizontal Microprogrammed Processor

Problem Statement

A microprogrammed control unit must support $256$ distinct machine instructions. Statistical profiling reveals that each instruction requires an average of $16$ micro-operations.

The hardware architecture has the following specifications:

• The system must test $16$ distinct status flag conditions for conditional branching.
• The execution datapath requires $48$ individual, independent control signals.
• Horizontal microprogramming is employed with a single-address field format for branch control logic.

Determine:

1. The total number of words required in Control Memory.
2. The number of bits required in the Control Address Register (CAR).
3. The bit-width of each field (Control, Condition, Next Address) and the total width of the micro-instruction control word.
4. The total capacity of the Control Memory expressed in both bits and Bytes.

Step-by-Step Solution

1. Total Words in Control Memory: The total number of micro-instructions that must be stored across all 256 instruction routines is:

$$\text{Total Micro-instructions} = 256 \text{ instructions} \times 16 \frac{\text{micro-operations}}{\text{instruction}} = 4096 \text{ words}$$ $$\mathbf{\text{Control Memory Depth}} = 4096 \text{ words} = 2^{12} \text{ words}$$

2. Bit-Width of Control Address Register (CAR): To uniquely address $4096$ memory locations:

$$\mathbf{\text{CAR Width}} = \log_2(4096) = \log_2(2^{12}) = \mathbf{12 \text{ bits}}$$

3. Field Allocation of the Micro-Instruction Control Word: In a single-address format, the control word consists of three fields:

• Control Signal Field: Horizontal microprogramming assigns $1 \text{ bit}$ per control signal. For 48 control signals:

  $$\text{Control Field Width} = 48 \text{ bits}$$

• Condition / Status Select Field: To select one of 16 status flags via a multiplexer:

  $$\text{Condition Field Width} = \lceil \log_2(16) \rceil = 4 \text{ bits}$$

• Next Address Field: Must hold a complete Control Memory address to execute conditional branches:

  $$\text{Address Field Width} = 12 \text{ bits}$$

Total Control Word Width:

$$\mathbf{\text{Control Word Width}} = 48 + 4 + 12 = \mathbf{64 \text{ bits (8 Bytes)}}$$

4. Total Control Memory Capacity:

$$\text{Capacity (Bits)} = 4096 \text{ words} \times 64 \text{ bits/word} = \mathbf{262,144 \text{ bits}}$$ $$\mathbf{\text{Capacity (Bytes)}} = \frac{262,144 \text{ bits}}{8 \text{ bits/Byte}} = 32,768 \text{ Bytes} = \mathbf{32 \text{ KB}}$$

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Example 2: Vertical Microprogramming Grouping & Bit Compression Analysis

Problem Statement

A processor control unit requires $70$ distinct control signals. Detailed timing and datapath analysis reveals that these signals can be partitioned into $10$ mutually exclusive groups, such that within any group, at most one signal is ever active during any clock cycle.

The number of signals assigned to each group is specified as follows:

Group	$G_1$	$G_2$	$G_3$	$G_4$	$G_5$	$G_6$	$G_7$	$G_8$	$G_9$	$G_{10}$
Number of Signals ($k_i$)	$3$	$12$	$7$	$5$	$11$	$11$	$14$	$3$	$5$	$3$

1. Calculate the number of bits required for each group's field in the vertical micro-instruction word (accounting for the inactive / NOP state).
2. Calculate the total number of bits required in the vertical control signal field.
3. Compare this with the bit requirement of a pure horizontal control field, and determine the bit compression ratio achieved by vertical encoding.

Step-by-Step Solution

1. Bit Width Derivation per Group: Each group of $k_i$ signals requires an idle state (NOP), requiring $\lceil \log_2(k_i + 1) \rceil$ bits:

• Group $G_1$: $k_1 = 3 \implies 3 + 1 = 4 \text{ states} \implies \lceil \log_2 4 \rceil = \mathbf{2 \text{ bits}}$
• Group $G_2$: $k_2 = 12 \implies 12 + 1 = 13 \text{ states} \implies \lceil \log_2 13 \rceil = \mathbf{4 \text{ bits}}$
• Group $G_3$: $k_3 = 7 \implies 7 + 1 = 8 \text{ states} \implies \lceil \log_2 8 \rceil = \mathbf{3 \text{ bits}}$
• Group $G_4$: $k_4 = 5 \implies 5 + 1 = 6 \text{ states} \implies \lceil \log_2 6 \rceil = \mathbf{3 \text{ bits}}$
• Group $G_5$: $k_5 = 11 \implies 11 + 1 = 12 \text{ states} \implies \lceil \log_2 12 \rceil = \mathbf{4 \text{ bits}}$
• Group $G_6$: $k_6 = 11 \implies 11 + 1 = 12 \text{ states} \implies \lceil \log_2 12 \rceil = \mathbf{4 \text{ bits}}$
• Group $G_7$: $k_7 = 14 \implies 14 + 1 = 15 \text{ states} \implies \lceil \log_2 15 \rceil = \mathbf{4 \text{ bits}}$
• Group $G_8$: $k_8 = 3 \implies 3 + 1 = 4 \text{ states} \implies \lceil \log_2 4 \rceil = \mathbf{2 \text{ bits}}$
• Group $G_9$: $k_9 = 5 \implies 5 + 1 = 6 \text{ states} \implies \lceil \log_2 6 \rceil = \mathbf{3 \text{ bits}}$
• Group $G_{10}$: $k_{10} = 3 \implies 3 + 1 = 4 \text{ states} \implies \lceil \log_2 4 \rceil = \mathbf{2 \text{ bits}}$

2. Total Vertical Control Field Width: Sum the bits across all 10 encoded groups:

$$\text{Total Vertical Bits} = 2 + 4 + 3 + 3 + 4 + 4 + 4 + 2 + 3 + 2 = \mathbf{31 \text{ bits}}$$

3. Compression Comparison:

• Horizontal Control Width:

  $$\text{Total Signals} = \sum_{i=1}^{10} k_i = 3+12+7+5+11+11+14+3+5+3 = 74 \text{ bits}$$

• Bit Reduction:

  $$\text{Bits Saved} = 74 - 31 = 43 \text{ bits}$$

• Compression Ratio:

  $$\text{Compression Ratio} = \frac{\text{Horizontal Bits}}{\text{Vertical Bits}} = \frac{74}{31} \approx \mathbf{2.39 : 1}$$

Vertical microprogramming achieves a $58.11\%$ reduction in the control field width, drastically shrinking control memory silicon footprint at the expense of adding ten small decoders ($2 \times 4, 3 \times 8, 4 \times 16$) at the output stage.

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Example 3: Microinstruction Field Allocation & CAR Sizing

Problem Statement

A processor architecture has the following two microprogrammed control unit design specifications:

Part A: A CPU executes an instruction set of $140$ instructions, where every instruction requires exactly $7$ clock cycles to execute. The control unit must generate $125$ distinct control signals. A horizontal microprogrammed control unit is designed using a single-address field format for branch control logic. Calculate the minimum size of the Control Word and the Control Address Register (CAR).

Part B: The microinstructions stored in the control memory of a processor have a total width of $26 \text{ bits}$. Each microinstruction is divided into three fields:

• A micro-operation field of $13 \text{ bits}$.
• A next-address field of $X \text{ bits}$.
• A MUX select field of $Y \text{ bits}$.

There are $8$ status bits connected to the inputs of the condition multiplexer. Calculate the values of $X$ and $Y$, and determine the maximum size of the Control Memory in number of words.

Step-by-Step Solution

Part A Solution:

1. Calculate total micro-instructions across all routines:

   $$N_{\text{micro}} = 140 \text{ instructions} \times 7 \frac{\text{cycles}}{\text{instruction}} = 980 \text{ micro-instructions}$$

2. Calculate CAR width: Since $2^9 = 512 < 980 \le 1024 = 2^{10}$:

   $$\mathbf{\text{CAR Width}} = \lceil \log_2 980 \rceil = \mathbf{10 \text{ bits}}$$

3. Calculate Control Word width: Horizontal microprogramming uses $1 \text{ bit}$ per control signal ($125 \text{ bits}$), and the single-address field matches the CAR width ($10 \text{ bits}$):

   $$\mathbf{\text{Control Word Width}} = 125 + 10 = \mathbf{135 \text{ bits}}$$

The minimum size of the Control Word is $135 \text{ bits}$, and the Control Address Register is $10 \text{ bits}$.

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Part B Solution:

1. Determine MUX select field ($Y$): The condition multiplexer selects among $8$ status bits:

   $$\mathbf{Y} = \lceil \log_2 8 \rceil = \mathbf{3 \text{ bits}}$$

2. Determine next-address field ($X$): The total microinstruction width is 26 bits:

   $$\text{Total Width} = \text{Micro-op Field} + X + Y$$ $$26 = 13 + X + 3 \implies 26 = 16 + X \implies \mathbf{X = 10 \text{ bits}}$$

3. Determine Control Memory size in number of words: With an address field of $X = 10 \text{ bits}$, the control memory can address:

   $$\mathbf{\text{Control Memory Capacity}} = 2^X = 2^{10} = \mathbf{1024 \text{ words}}$$

Summary of Part B: $X = 10 \text{ bits}$, $Y = 3 \text{ bits}$, and Control Memory size is $1024 \text{ words}$.

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🎯 Exam & Interview Pitfall Check

Core Conceptual Questions

1. Why is an extra NOP state strictly mandatory when grouping control signals in vertical microprogramming?

   • In any given clock cycle, a particular functional group (e.g., ALU operations or Memory write operations) might not need to perform any action at all. If a field of $k$ signals is encoded using $\lceil \log_2 k \rceil$ bits without an idle code, the decoder will constantly assert one of the $k$ control signals in every cycle, causing catastrophic unintended hardware operations. The $+1$ state allows code $00\dots0_2$ to represent "No Operation (NOP)".

2. What is the functional difference between the Program Counter (PC) and the Control Address Register (CAR)?

   • The Program Counter (PC) holds the main memory address of the next machine instruction (macro-instruction) in the user's program. The Control Address Register (CAR) holds the internal Control Memory (ROM) address of the next micro-instruction within the microcode routine executing the current machine instruction.

3. How does Nano-programming achieve such dramatic memory savings in complex processors?

   • In CISC processors with wide control words ($100+ \text{ bits}$), most micro-instructions repeat identical control combinations. Nano-programming separates sequencing from control pattern generation: Level 1 ($\mu$ROM) stores only short pointers (nano-addresses) and branch targets, while Level 2 (NanoROM) stores a single master copy of each unique horizontal control vector, eliminating repetitive wide-word storage.

Common Interview Traps

• Trap 1: Forgetting to add 1 for NOP when calculating vertical field bit-widths.
  • If a group has $8$ signals, calculating $\log_2(8) = 3 \text{ bits}$ is incorrect! Eight signals plus one NOP state equals $9$ states, which requires $\lceil \log_2(9) \rceil = \mathbf{4 \text{ bits}}$. Forgetting the NOP state is the single most common numerical error in control unit examinations.
• Trap 2: Confusing microcode patchability with software application execution.
  • While microcode can be updated by OS kernel patches to fix CPU hardware errata, microcode does not execute out of standard DRAM main memory. It is loaded into high-speed on-die static RAM (SRAM) registers within the CPU control unit that intercept instruction decoding.
• Trap 3: Assuming vertical microprogramming allows multiple signals from the same group to be active simultaneously.
  • By definition, a single $k$-bit field decoded by an $k \times 2^k$ binary decoder can activate at most one output line at any time. If two control signals must ever be asserted in the same clock cycle, they cannot be placed in the same vertical group!

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