6.3 D and T Flip-Flops: Conversion & Excitation Tables

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📚Module 06: Sequential Logic Circuits: Latches & Flip-FlopsTopic 6.3⏱️20 min read

🎯High-Yield For:University Semester Exams • Hardware Engineering Rounds • Foundational Computing

💡 Core Intuition: The Data Camera vs. The Tally Clicker

While SR and JK flip-flops are versatile, modern digital processors overwhelmingly standardize on two specialized variants:

🍳 The Everyday Analogy: The Photo Snapshot vs. The Subway Turnstile Counter

• The D Flip-Flop (The High-Speed Shutter): Imagine a sports photographer with a camera shutter that opens for a fraction of a millisecond. Whatever image is present in front of the lens at the moment the button clicks is frozen on digital film. Even if the runner sprints away a second later, the captured frame remains identical until the next shutter click.
• The T Flip-Flop (The Subway Turnstile Gate): Imagine a subway turnstile with a binary flip bar. Every single time an authorized passenger pushes the bar ($T = 1$), the state alternates: Locked $\to$ Unlocked $\to$ Locked. If no passenger pushes ($T = 0$), the bar preserves its state.

💻 Bridging to Computer Science

In computer systems engineering and VLSI hardware:

1. Instruction Pipeline Registers: Modern out-of-order execution CPU cores (Intel, AMD, Apple Silicon) place banks of 64-bit and 128-bit D Flip-Flops between pipeline stages (Fetch, Decode, Rename, Dispatch, Execute, Writeback).
2. Frequency Division & Prescalers: By fixing $T=1$, each output cycle requires two input clock cycles. Cascading $n$ T flip-flops divides the master clock frequency by $2^n$ ($f_{out} = f_{CLK}/2^n$), enabling lower-frequency peripheral clocks from high-speed CPU PLLs.
3. Static Timing Analysis (STA): Silicon synthesis engines enforce strict Setup Time ($t_{su}$) and Hold Time ($t_h$) constraints on every D flip-flop data pin to ensure timing closure at gigahertz frequencies.

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📑Table of Contents

• ⏱️ The D Flip-Flop (Architecture & Timing)
  • Why the D Flip-Flop is Structurally Bulletproof:
  • ⏱️ Critical Dynamic Timing Constraints: Setup & Hold Times
• 🔄 The T Flip-Flop & Frequency Division
  • Functional Operation:
  • 📈 Binary Frequency Division:
• 📊 Master Matrix: Truth, Characteristic & Excitation Tables
  • Comprehensive Flip-Flop Master Comparison
• ⚙️ The Universal 4-Step Flip-Flop Conversion Algorithm
  • The 4-Step Framework:
• 🔬 Comprehensive Conversion Derivations & K-Maps
  • Case Study 1: Convert an Available JK Flip-Flop into a D Flip-Flop
  • Case Study 2: Convert an Available SR Flip-Flop into a JK Flip-Flop
  • Case Study 3: Convert an Available JK Flip-Flop into a T Flip-Flop
• 🏭 Real-World Production Context: Timing Closure & Metastability in Modern SOCs
• 📐 Numerical Applications & Worked Examples
  • Example 1: Critical Path Timing & Maximum Operating Frequency Calculation
  • Example 2: Conversion of an Available SR Flip-Flop into a Target D Flip-Flop
  • Example 3: Conversion of an Available D Flip-Flop into a Target T Flip-Flop
• 🎯 Exam & Interview Pitfall Check

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⏱️ The D Flip-Flop (Architecture & Timing)

The D Flip-Flop (also called a Data or Delay Flip-Flop) eliminates the dual-input complexity of the SR latch by driving $S$ and $R$ from a single input pin $D$, with an inverter placed between them:

• $S = D$
• $R = \bar{D}$

D Flip-Flop (Single-Bit Storage Core)Click Clock to Sample D

📦

DATA LATCHING: On the rising clock edge, the value present at D is transferred directly to output Q. Characteristic Equation: Q(next) = D.

D Flip-Flop Excitation & Truth Table

CLK	D	Qn	Qn+1	Operation
0	×	0	0	Hold (No Trigger)
↑	0	0	0	Reset (Sample 0)
↑	1	0	1	Set (Sample 1)

Why the D Flip-Flop is Structurally Bulletproof:

Because $R$ is always the strict logical complement of $S$:

1. If $D = 1 \implies S = 1, R = 0 \implies \mathbf{SET} \, (Q = 1)$.
2. If $D = 0 \implies S = 0, R = 1 \implies \mathbf{RESET} \, (Q = 0)$.
3. The $SR = 11$ forbidden condition can NEVER occur (since $D$ cannot be simultaneously $1$ and $0$).
4. The $SR = 00$ indeterminate condition can NEVER occur.

📐D Flip-Flop Characteristic Equationformula

$$Q_{next} = D$$

The next state is unconditionally equal to the data present on $D$ at the sampling clock edge.

⏱️ Critical Dynamic Timing Constraints: Setup & Hold Times

In ideal theory, sampling is instantaneous. In physical silicon, transistors require a non-zero time to charge internal parasitic capacitances:

Architecture Flow

Synchronous Dynamic Timing Constraints

Temporal stability windows required around the active clock edge to guarantee deterministic latching

Pre-Clock

Setup Window (t_su)

Stable BEFORE Clock Edge

Data D must stay constant for at least t_su before the clock edge to charge internal master capacitances.

→

Clock arrives

Trigger

Active Clock Edge (↑)

Sampling Event

Trigger threshold crossed. Transistor gates switch state to capture current input value.

→

Latch locks

Post-Clock

Hold Window (t_h)

Stable AFTER Clock Edge

Data D must be held stable for t_h after the edge to prevent early data transitions from corrupting the latch.

→

Output propagates

Output

Clock-to-Q Delay (t_cq)

Output Valid Delay

Time required for internal latched charge to drive output pad Q to a valid voltage rail (VOL or VOH).

1. Setup Time ($t_{su}$): The minimum time the data input $D$ must remain stable and constant BEFORE the arrival of the active clock edge. If $D$ changes within $t_{su}$, the internal feedback loop will catch a split-rail voltage, plunging the flip-flop into metastability.
2. Hold Time ($t_h$): The minimum time the data input $D$ must remain stable and constant AFTER the active clock edge has struck. If $D$ changes before $t_h$ expires, the new data will corrupt the currently latching bit.
3. Clock-to-Q Propagation Delay ($t_{cq}$): The time elapsed from the active clock edge until the output terminal $Q$ physically stabilizes at its valid logic level.

📐Maximum Clock Frequency of a Synchronous Digital Pipelineformula

$$T_{CLK} \ge t_{cq} + t_{comb(max)} + t_{su} \implies f_{max} = \frac{1}{T_{CLK(min)}}$$

Where $t_{comb(max)}$ is the worst-case propagation delay of the combinational logic cloud (ALU, adder, MUX) between two flip-flops.

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🔄 The T Flip-Flop & Frequency Division

The T Flip-Flop (Toggle Flip-Flop) is constructed by taking a JK flip-flop and physically tying its two inputs together: $J = K = T$

T Flip-Flop (Frequency Divider)Click Clock to Toggle

🔁

FREQUENCY DIVISION: With T=1, output Q changes state once every clock period, creating an exact divide-by-2 square wave (f_Q = f_CLK / 2). Characteristic Equation: Q(next) = T ⊕ Q.

T Flip-Flop Characteristic Table

CLK	T	Qn	Qn+1	Resulting Action
↑	0	0	0	Hold (No Change)
↑	1	0	1	Toggle State ($Q \leftarrow Q'$)

Functional Operation:

1. When $T = 0 \implies J = 0, K = 0$: The flip-flop enters the HOLD mode ($Q_{next} = Q$).
2. When $T = 1 \implies J = 1, K = 1$: The flip-flop enters the TOGGLE mode ($Q_{next} = \bar{Q}$).

📐T Flip-Flop Characteristic Equationformula

$$Q_{next} = T\bar{Q} + \bar{T}Q = T \oplus Q$$

📈 Binary Frequency Division:

When $T = 1$ is held continuously high, output $Q$ inverts on every rising clock edge. Therefore, it takes two complete clock cycles for $Q$ to execute one full $0 \to 1 \to 0$ period:

📐Clock Frequency Halvingformula

$$f_{Q} = \frac{f_{CLK}}{2} \quad \text{and} \quad T_Q = 2 \cdot T_{CLK}$$

Cascading $N$ T Flip-Flops in series creates a divide-by-$2^N$ clock divider and a binary ripple counter!

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📊 Master Matrix: Truth, Characteristic & Excitation Tables

Understanding the fundamental distinction between a Characteristic Table and an Excitation Table is vital for digital hardware design:

• Characteristic Table: Answers: "Given current state $Q_n$ and inputs, what will next state $Q_{n+1}$ be?" (Used for circuit ANALYSIS).
• Excitation Table: Answers: "Given current state $Q_n$ and desired target state $Q_{n+1}$, what inputs must we apply?" (Used for circuit DESIGN & SYNTHESIS).

Comprehensive Flip-Flop Master Comparison

Flip-Flop Type	Characteristic Equation	Inputs	Excitation: $0 \to 0$	Excitation: $0 \to 1$	Excitation: $1 \to 0$	Excitation: $1 \to 1$
SR	$Q_{next} = S + \bar{R}Q \, (SR=0)$	$S, R$	$S=0, R=\times$	$S=1, R=0$	$S=0, R=1$	$S=\times, R=0$
JK	$Q_{next} = J\bar{Q} + \bar{K}Q$	$J, K$	$J=0, K=\times$	$J=1, K=\times$	$J=\times, K=1$	$J=\times, K=0$
D	$Q_{next} = D$	$D$	$D=0$	$D=1$	$D=0$	$D=1$
T	$Q_{next} = T \oplus Q$	$T$	$T=0$	$T=1$	$T=1$	$T=0$

(Note: $\times$ denotes a Don't-Care condition, meaning the input can be either $0$ or $1$ without affecting the transition).

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⚙️ The Universal 4-Step Flip-Flop Conversion Algorithm

In exams and technical interviews, you will frequently be asked to convert one flip-flop type into another (e.g., "Convert an available JK flip-flop into a D flip-flop").

Follow this universal algorithmic framework:

Universal 4-Step Flip-Flop Conversion Algorithm

Algorithmic pipeline to convert any given flip-flop into any desired target flip-flop

1

Step 1: Identify Target & Available Flip-Flops

Roles Definition

Define the Target (Required) device whose inputs are given, and the Available (Physical) hardware whose inputs must be synthesized.

Target = Desired Behavior | Available = Silicon Hardware

2

Step 2: Construct the Combined Conversion Table

Excitation Mapping

List Target Inputs + Present State (Qn), evaluate Next State (Qn+1), then look up Available excitation table to find required inputs.

Columns: [Target In] | Qn | Qn+1 | [Available In]

3

Step 3: K-Map Minimization for Available Inputs

Boolean Reduction

Plot each Available flip-flop input as a function of [Target In, Qn]. Exploit Don't-Care (X) conditions for maximum gate reduction.

F_avail = f(Target_Inputs, Qn) via K-Map

4

Step 4: Synthesize Combinational Driving Circuit

Circuit Schematic

Connect minimized combinational logic from target inputs and feedback Qn into the available flip-flop terminals.

Target Inputs + Qn → Combinational Gates → Available FF

The 4-Step Framework:

1. Identify Roles:
   • Required (Target) Flip-Flop: The device whose behavior we want to mimic (e.g., D-FF).
   • Available (Given) Flip-Flop: The physical silicon hardware we have in stock (e.g., JK-FF).
2. Construct the Conversion Table:
   • List all combinations of Target Inputs and Present State ($Q_n$).
   • Determine the Next State ($Q_{n+1}$) using the Target Flip-Flop's characteristic behavior.
   • Look up the Excitation Requirements of the Available Flip-Flop to transition from $Q_n \to Q_{n+1}$.
3. K-Map Minimization:
   • Treat the Available Flip-Flop inputs as the dependent output functions.
   • Solve K-Maps in terms of Target Inputs and $Q_n$, taking full advantage of don't-care ($\times$) conditions.
4. Schematic Implementation:
   • Wire the minimized combinational logic into the inputs of the available flip-flop.

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🔬 Comprehensive Conversion Derivations & K-Maps

Let us work through the most high-yield flip-flop conversions step-by-step:

Case Study 1: Convert an Available JK Flip-Flop into a D Flip-Flop

• Given (Available): JK Flip-Flop.
• Target (Required): D Flip-Flop.

Conversion Table:

Target Input $D$	Present State $Q_n$	Next State $Q_{n+1}$	Required $J$ (Excitation)	Required $K$ (Excitation)
$0$	$0$	$0$	$0$	$\times$
$0$	$1$	$0$	$\times$	$1$
$1$	$0$	$1$	$1$	$\times$
$1$	$1$	$1$	$\times$	$0$

K-Map for $J$:

• Input variables: $D, Q_n$.
• $J(D=0, Q_n=0) = 0$
• $J(D=0, Q_n=1) = \times$
• $J(D=1, Q_n=0) = 1$
• $J(D=1, Q_n=1) = \times$
• Grouping the $1$ with the $\times$ in row $D=1$: $\mathbf{J = D}$

K-Map for $K$:

• $K(D=0, Q_n=0) = \times$
• $K(D=0, Q_n=1) = 1$
• $K(D=1, Q_n=0) = \times$
• $K(D=1, Q_n=1) = 0$
• Grouping the $1$ with the $\times$ in row $D=0$: $\mathbf{K = \bar{D}}$

Realization: Connect $D$ directly to input $J$, and connect $\bar{D}$ (via a NOT gate) to input $K$!

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Case Study 2: Convert an Available SR Flip-Flop into a JK Flip-Flop

• Given (Available): SR Flip-Flop.
• Target (Required): JK Flip-Flop.

Conversion Table:

$J$	$K$	$Q_n$	$Q_{n+1}$	Required $S$	Required $R$
$0$	$0$	$0$	$0$	$0$	$\times$
$0$	$0$	$1$	$1$	$\times$	$0$
$0$	$1$	$0$	$0$	$0$	$\times$
$0$	$1$	$1$	$0$	$0$	$1$
$1$	$0$	$0$	$1$	$1$	$0$
$1$	$0$	$1$	$1$	$\times$	$0$
$1$	$1$	$0$	$1$	$1$	$0$
$1$	$1$	$1$	$0$	$0$	$1$

K-Map for $S$:

• Plotting $S(J, K, Q_n)$: 1s occur at $m_4, m_6$; $\times$ at $m_1, m_5$.
• Grouping $m_4, m_6$: $\mathbf{S = J\bar{Q}}$

K-Map for $R$:

• Plotting $R(J, K, Q_n)$: 1s occur at $m_3, m_7$; $\times$ at $m_0, m_2$.
• Grouping $m_3, m_7$: $\mathbf{R = KQ}$

Realization:

• $S$ is driven by an AND gate receiving $J$ and $\bar{Q}$.
• $R$ is driven by an AND gate receiving $K$ and $Q$. (This matches the internal architecture of the JK flip-flop derived in Topic 6.2!)

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Case Study 3: Convert an Available JK Flip-Flop into a T Flip-Flop

• Given (Available): JK Flip-Flop.
• Target (Required): T Flip-Flop.

Conversion Table:

Target $T$	Present State $Q_n$	Next State $Q_{n+1}$	Required $J$	Required $K$
$0$	$0$	$0$	$0$	$\times$
$0$	$1$	$1$	$\times$	$0$
$1$	$0$	$1$	$1$	$\times$
$1$	$1$	$0$	$\times$	$1$

Minimization:

• For $J$: Combining $1$ at $(T=1, Q=0)$ with don't-care $\times$ at $(T=1, Q=1) \implies \mathbf{J = T}$.
• For $K$: Combining $1$ at $(T=1, Q=1)$ with don't-care $\times$ at $(T=1, Q=0) \implies \mathbf{K = T}$.

Realization: Tie $J$ and $K$ together and connect them to input $T$ ($\mathbf{J = K = T}$).

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🏭 Real-World Production Context: Timing Closure & Metastability in Modern SOCs

In multimillion-gate System-on-Chip (SoC) designs:

• Timing Closure: Synthesis compilers (Synopsys Design Compiler, Cadence Genus) calculate the critical path delay between launch and capture D flip-flops: $T_{CLK} \ge t_{cq} + t_{comb(max)} + t_{su}$. If physical wire delay or gate depth causes data to arrive within $t_{su}$, setup slack becomes negative, causing timing violations.
• Metastability Protection: When asynchronous sensor lines cross clock domains, dual-stage D flip-flop synchronizers (MTBF synchronizers) provide exponential protection against metastable mid-rail latching.

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📐 Numerical Applications & Worked Examples

Example 1: Critical Path Timing & Maximum Operating Frequency Calculation

Problem Statement:
A synchronous digital pipeline contains two sequential registers built of positive edge-triggered D flip-flops, separated by an arithmetic combinational logic block. The timing parameters from standard cell datasheets are:

• Flip-flop clock-to-Q delay: $t_{cq} = 1.2\text{ ns}$
• Flip-flop setup time: $t_{su} = 0.8\text{ ns}$
• Flip-flop hold time: $t_h = 0.4\text{ ns}$
• Combinational logic path delay: $t_{comb(max)} = 3.0\text{ ns}$, $t_{comb(min)} = 0.6\text{ ns}$
• Clock skew between launch and capture registers: $t_{skew} = 0.2\text{ ns}$

1. Calculate the minimum allowable clock period $T_{CLK(min)}$ and the maximum operating clock frequency $f_{max}$.
2. Verify whether the hold time constraint is satisfied.

Step-by-Step Solution:

1. Setup Time Constraint & Clock Period:
   • For the capture flip-flop to reliably latch data on the next clock edge:
     $T_{CLK} + t_{skew} \ge t_{cq} + t_{comb(max)} + t_{su}$
     $T_{CLK(min)} = t_{cq} + t_{comb(max)} + t_{su} - t_{skew}$
     $T_{CLK(min)} = 1.2\text{ ns} + 3.0\text{ ns} + 0.8\text{ ns} - 0.2\text{ ns} = 4.8\text{ ns}$
2. Calculate Maximum Operating Clock Frequency:
   $f_{max} = \frac{1}{T_{CLK(min)}} = \frac{1}{4.8 \times 10^{-9}\text{ s}} \approx 208.33\text{ MHz}$
3. Verify Hold Time Constraint:
   • The minimum delay through the launch flip-flop and combinational logic must exceed the hold time plus clock skew:
     $t_{cq} + t_{comb(min)} \ge t_h + t_{skew}$
     $\text{LHS} = 1.2\text{ ns} + 0.6\text{ ns} = 1.8\text{ ns}$
     $\text{RHS} = 0.4\text{ ns} + 0.2\text{ ns} = 0.6\text{ ns}$
   • Because $1.8\text{ ns} \ge 0.6\text{ ns}$, the hold constraint is satisfied with a positive hold slack of $+1.2\text{ ns}$. No hold violations exist.

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Example 2: Conversion of an Available SR Flip-Flop into a Target D Flip-Flop

Problem Statement:
Using the universal 4-step flip-flop conversion algorithm, design a combinational driving circuit that converts a standard available SR flip-flop into a D flip-flop. Show the conversion table, derive the minimal excitation equations for $S$ and $R$, and draw the resulting realization.

Step-by-Step Solution:

1. Identify Target & Available Devices:

   • Target (Required): D Flip-Flop (Input: $D$, behavior: $Q_{n+1} = D$).
   • Available (Given): SR Flip-Flop (Inputs: $S, R$).

2. Construct Combined Conversion Table:
   Map target input $D$ and present state $Q_n$ to next state $Q_{n+1}$, then consult the SR excitation table:

   Target $D$	Present State $Q_n$	Next State $Q_{n+1}$	Required $S$	Required $R$
   0	0	0	0	$\times$
   0	1	0	0	1
   1	0	1	1	0
   1	1	1	$\times$	0

3. K-Map Minimization for $S$ and $R$:

   • For $S$ (functions of $D, Q_n$):
     $m(D=1, Q_n=0) = 1$, with don't-care at $(D=1, Q_n=1)$.
     Group cell 2 and cell 3:
     $\mathbf{S = D}$
   • For $R$ (functions of $D, Q_n$):
     $m(D=0, Q_n=1) = 1$, with don't-care at $(D=0, Q_n=0)$.
     Group cell 0 and cell 1:
     $\mathbf{R = \bar{D}}$

4. Circuit Realization:
   Connect input $D$ directly to terminal $S$, and pass $D$ through an inverter (NOT gate) to terminal $R$. This mathematically reproduces the standard D flip-flop architecture.

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Example 3: Conversion of an Available D Flip-Flop into a Target T Flip-Flop

Problem Statement:
Convert an available D flip-flop into a T flip-flop using the 4-step framework. Derive the minimal Boolean expression for input $D$ in terms of $T$ and present state $Q_n$.

Step-by-Step Solution:

1. Identify Target & Available Devices:

   • Target: T Flip-Flop (Input: $T$, characteristic: $Q_{n+1} = T \oplus Q_n$).
   • Available: D Flip-Flop (Input: $D$, characteristic: $Q_{n+1} = D$).

2. Construct Combined Conversion Table:

   Target $T$	Present State $Q_n$	Next State $Q_{n+1}$	Required $D$ ($D = Q_{n+1}$)
   0	0	0	0
   0	1	1	1
   1	0	1	1
   1	1	0	0

3. Derive Minimized Expression for $D$:

   • Notice that $D = 1$ when $(T=0, Q_n=1)$ and $(T=1, Q_n=0)$.
   • Sum of Products:
     $D = T \bar{Q}_n + \bar{T} Q_n = \mathbf{T \oplus Q_n}$

4. Circuit Realization:
   Place a 2-input XOR gate at the data terminal $D$. Connect input $T$ to one input of the XOR gate and feed current output $Q_n$ back into the second input ($D = T \oplus Q$). This realizes a frequency-dividing toggle cell.

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🎯 Exam & Interview Pitfall Check

Core Conceptual Questions

• Why are modern CPU pipeline registers built almost exclusively using D Flip-Flops rather than JK or SR Flip-Flops?
  Silicon area and routing economy! A D flip-flop requires only a single routing track per data bit, whereas JK and SR flip-flops require two separate signal lines per bit. Across a 64-bit wide datapath with 20 pipeline stages, using D flip-flops saves thousands of metal interconnect tracks, drastically minimizing capacitive dynamic power dissipation.
• What occurs if the Setup Time ($t_{su}$) or Hold Time ($t_h$) is violated in an ASIC design?
  The flip-flop enters Metastability: internal transistors fail to resolve to either $V_{DD}$ or $GND$ within the clock cycle, lingering at a mid-rail indeterminate voltage. Downstream logic gates may interpret this as a $0$ or $1$ inconsistently, causing catastrophic system crashes or memory corruption.

Common Interview Traps

• Trap: Forgetting that Excitation Tables contain Don't-Cares ($\times$).
  In the transition $0 \to 0$ for a JK flip-flop, candidates often answer $J=0, K=0$. While $00$ works (Hold), $J=0, K=1$ (Reset) ALSO transitions $0 \to 0$! Therefore, the correct excitation is $J=0, K=\mathbf{\times}$. Omitting don't-cares results in suboptimal, bloated combinational conversion circuits.
• Trap: Confusing the $0 \to 1$ transition in SR vs JK Flip-Flops.
  For an SR flip-flop, transitioning from $0 \to 1$ strictly requires $S=1, R=0$ (no don't-care is permitted on $R$ because $R=1$ is forbidden). For a JK flip-flop, transitioning from $0 \to 1$ requires $J=1, K=\mathbf{\times}$ (since $K=1$ toggle also reaches 1).

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🗺️View Complete Digital Logic Roadmap & Syllabus

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